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ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
15 years 8 months ago
Logic design for low-voltage/low-power CMOS circuits
Christian Piguet, Jean-Marc Masgonty, V. von Kaene...
ISLPED
1995
ACM
129views Hardware» more  ISLPED 1995»
15 years 8 months ago
CMOS dynamic power estimation based on collapsible current source transistor modeling
When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Pet...
ISLPED
1995
ACM
122views Hardware» more  ISLPED 1995»
15 years 8 months ago
A multiple clocking scheme for low power RTL design
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
Christos A. Papachristou, Mark Spining, Mehrdad No...
127
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ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 8 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
15 years 8 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm