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ISCA
1995
IEEE
133views Hardware» more  ISCA 1995»
15 years 8 months ago
Performance Evaluation of the PowerPC 620 Microarchitecture
The PowerPC 620TM microprocessor1 is the most recent and performance leading member of the PowerPCTM family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch predi...
Trung A. Diep, Christopher Nelson, John Paul Shen
ISCA
1995
IEEE
109views Hardware» more  ISCA 1995»
15 years 8 months ago
Next Cache Line and Set Prediction
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald
149
Voted
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 8 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 8 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 8 months ago
Unconstrained Speculative Execution with Predicated State Buffering
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masa...