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ISCAS
1995
IEEE
77views Hardware» more  ISCAS 1995»
15 years 8 months ago
Exploration of Area and Performance Optimized Datapath Design Using Realistic Cost Metrics
We present a novel technique for datapath allocation, which incorporates interconnection area and delay estimates based on dynamic oorplanning. In this approach, datapath area is ...
Kyumyung Choi, Steven P. Levitan
ISCAS
1995
IEEE
83views Hardware» more  ISCAS 1995»
15 years 8 months ago
Analog Filter Banks with Low Intermodulation Distortion
It is demonstrated that the filter-bank structure of [1] can be designed to significantly reduce the effect of intermodulation distortion. This gives it an important advantage o...
James A. Cherry, W. Martin Snelgrove
94
Voted
ISCAS
1995
IEEE
107views Hardware» more  ISCAS 1995»
15 years 8 months ago
A 3-D Integrator-Differentiator Double-Loop (IDD) Filter for Raster-Scan Video Processing
R. K. Bertschmann, N. R. Bartley, Leonard T. Bruto...
121
Voted
SAC
1997
ACM
15 years 8 months ago
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
ISCAS
1995
IEEE
107views Hardware» more  ISCAS 1995»
15 years 8 months ago
Power Dissipation in Deep Submicron CMOS Digital Circuits
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
R. X. Gu, Mohamed I. Elmasry