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DFT
2004
IEEE
94views VLSI» more  DFT 2004»
15 years 7 months ago
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n1, m, 3) convolutional...
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman ...
DFT
2004
IEEE
78views VLSI» more  DFT 2004»
15 years 7 months ago
Reliability Modeling and Assurance of Clockless Wave Pipeline
This paper presents theoretical yet practical methodologies to model, assure and optimize the Reliability of Clockless Wave Pipeline. Clockless wave pipeline is a cutting-edge and...
T. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lomb...
128
Voted
DFT
2004
IEEE
95views VLSI» more  DFT 2004»
15 years 7 months ago
Mixed Loopback BiST for RF Digital Transceivers
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
Jerzy Dabrowski, Javier Gonzalez Bayon
148
Voted
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
15 years 7 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
127
Voted
DFT
2004
IEEE
102views VLSI» more  DFT 2004»
15 years 7 months ago
Exploiting an I-IP for In-Field SOC Test
Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza ...