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141
Voted
DATE
2004
IEEE
116views Hardware» more  DATE 2004»
15 years 7 months ago
Full-Chip Multilevel Routing for Power and Signal Integrity
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
Jinjun Xiong, Lei He
CBSE
2006
Springer
15 years 7 months ago
Virtualization of Service Gateways in Multi-provider Environments
Abstract. Today we see more and more services being brought to connected homes, such as entertainment or home automation. These services are published and operated by a variety of ...
Yvan Royon, Stéphane Frénot, Frederi...
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 7 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
119
Voted
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 7 months ago
Arithmetic Reasoning in DPLL-Based SAT Solving
We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an arithmetic bit level descrip...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 7 months ago
Thermal and Power Integrity Based Power/Ground Networks Optimization
With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects...
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Pin...