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134
Voted
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 7 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
125
Voted
DATE
2004
IEEE
141views Hardware» more  DATE 2004»
15 years 7 months ago
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors
Reconfigurable Systems-on-Chip (SoC) consist of large Field-Programmable Gate-Arrays (FPGAs) and standard processors. The reconfigurable logic can be used for application-specific...
Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Pao...
123
Voted
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 7 months ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
134
Voted
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
15 years 7 months ago
Cache-Aware Scratchpad Allocation Algorithm
In the context of portable embedded systems, reducing energy is one of the prime objectives. Most high-end embedded microprocessors include onchip instruction and data caches, alo...
Manish Verma, Lars Wehmeyer, Peter Marwedel
147
Voted
DATE
2004
IEEE
168views Hardware» more  DATE 2004»
15 years 7 months ago
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing
Energy efficient embedded systems consist of a heterogeneous collection of very specific building blocks, connected together by a complex network of many dedicated busses and inte...
Ingrid Verbauwhede, Patrick Schaumont, Christian P...