180
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
149
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical des...
148
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
One of the efficient design methodologies for large scale System on a Chip (SoC) is IP-based design. In this methodology, a system is considered as a set of components and intercon...
147
click to vote
ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Physical synthesis optimizations and engineering change orders typically change the locations of cells, resize cells or add more cells to the design after global placement. Unfort...
ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM