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VLSID
1995
IEEE

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Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

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Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

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In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free

Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng

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Multi-level Asynchronous Circuits | VLSI | VLSID 1995 |

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Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	VLSID
Authors	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng

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