Area efficient loop filter design for charge pump phase locked loop

In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25µ CSM

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: R. G. Raghavendra, Bharadwaj Amrutur
• Keywords: GLVLSI 2007, Loop Filter Circuits, Phase Locked Loop, VLSI