154
Voted
ICCAD
15 years 7 months ago
1991 IEEE 
This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
131
Voted
ICCAD
15 years 7 months ago
1991 IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
119
Voted
ICCAD
15 years 7 months ago
1991 IEEE 
In a high level synthesis environment there is a strong need for flexible module generators. For the generation of regular structures efficient dedicated module generators can be ...
116
Voted
ICCAD
15 years 7 months ago
1991 IEEE 107
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ICCAD
15 years 7 months ago
1991 IEEE 
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
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