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A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extend...

John W. Lockwood, Naji Naufel, Jonathan S. Turner,...

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191

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FPGA
2001
ACM

152views FPGA» more FPGA 2001»

A pipelined architecture for partitioned DWT based lossy image compression using FPGA's

15 years 10 months ago

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Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efﬁcient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...

Jörg Ritter, Paul Molitor

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154

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FPGA
2001
ACM

145views FPGA» more FPGA 2001»

Simultaneous logic decomposition with technology mapping in FPGA designs

15 years 10 months ago

Download cadlab.cs.ucla.edu

Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...

Gang Chen, Jason Cong

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133

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FPGA
2001
ACM

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The case for registered routing switches in field programmable gate arrays

15 years 10 months ago

Download www.eecg.toronto.edu

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Deshanand P. Singh, Stephen Dean Brown