FMCAD
15 years 4 months ago
2004 Springer 
The main challenge in BDD-based verification is dealing with the memory explosion problem during reachability analysis. In this paper we advocate a methodology to handle this probl...
106
Voted
FMCAD
15 years 4 months ago
2004 Springer 
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
109
Voted
FMCAD
15 years 4 months ago
2004 Springer 
Abstract. Probabilistic techniques for verification of finite-state transition systems offer huge memory savings over deterministic techniques. The two leading probabilistic scheme...
120
Voted
FMCAD
15 years 4 months ago
2004 Springer 
This work presents a memory-efficient All-SAT engine which, given a propositional formula over sets of important and non-important variables, returns the set of all the assignments...
FMCAD
15 years 5 months ago
2004 Springer 
We consider the problem of checking whether an incomplete design can still be extended to a complete design satisfying a given CTL formula and whether the property is satisfied fo...
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Formal Methods