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    PATMOS
    2004
    Springer
    195views Modeling and Simulation» more  PATMOS 2004»
    Optimal Logarithmic Representation in Terms of SNR Behavior
    13 years 11 months ago
    Optimal Logarithmic Representation in Terms of SNR Behavior
    Download  www.andrew.cmu.edu
    This paper investigates the Signal-to-Noise Ratio (SNR) performance of the Logarithmic Number System (LNS) representation against the SNR performance of the fixed-point representa...
    Panagiotis D. Vouzis, Vassilis Paliouras
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    PATMOS
    2004
    Springer
    156views Modeling and Simulation» more  PATMOS 2004»
    Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
    13 years 11 months ago
    Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
    Download  www.dice.ucl.ac.be
    A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...
    Ilham Hassoune, Amaury Nève, Jean-Didier Le...
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    PATMOS
    2004
    Springer
    149views Modeling and Simulation» more  PATMOS 2004»
    A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
    13 years 11 months ago
    A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
    Download  www.see.ed.ac.uk
    Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
    Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
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    PATMOS
    2004
    Springer
    138views Modeling and Simulation» more  PATMOS 2004»
    Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
    13 years 11 months ago
    Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
    Download  ce.et.tudelft.nl
    The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
    Peter Celinski, Derek Abbott, Sorin Cotofana
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    PATMOS
    2004
    Springer
    134views Modeling and Simulation» more  PATMOS 2004»
    An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design
    13 years 11 months ago
    An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design
    Download  www.ee.ucla.edu
    Motivated by very/ultra large scale integrated circuit (VLSI/ULSI) physical design applications, we study the construction of rectilinear minimum spanning tree (RMST) with its maxi...
    Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xia...
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