109
Voted
GLVLSI
15 years 6 months ago
2005 IEEE 
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
GLVLSI
15 years 6 months ago
2005 IEEE 
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
101
Voted
GLVLSI
15 years 6 months ago
2005 IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
108
Voted
GLVLSI
15 years 6 months ago
2005 IEEE
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
93
Voted
GLVLSI
15 years 6 months ago
2005 IEEE
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
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VLSI