146
Voted
ISPD
15 years 10 months ago
2010 ACM 
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
111
Voted
ISPD
15 years 10 months ago
2010 ACM  166
Voted
ISPD
15 years 10 months ago
2010 ACM 
Existing 3D placement techniques are mainly used for standardcell circuits, while mixed-size placement is needed to support highlevel functional units and intellectual property (I...
140
Voted
ISPD
15 years 10 months ago
2010 ACM 
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
140
Voted
ISPD
15 years 10 months ago
2010 ACM 
Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this paper we present FOARS, ...
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