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    178
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    225views Modeling and Simulation» more  PATMOS 2010»
    Clock Network Synthesis with Concurrent Gate Insertion
    15 years 4 months ago
    Clock Network Synthesis with Concurrent Gate Insertion
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    Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham
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    L1 Data Cache Power Reduction Using a Forwarding Predictor
    15 years 4 months ago
    L1 Data Cache Power Reduction Using a Forwarding Predictor
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    In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...
    P. Carazo, R. Apolloni, Fernando Castro, Daniel Ch...
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    Self-Timed SRAM for Energy Harvesting Systems
    15 years 4 months ago
    Self-Timed SRAM for Energy Harvesting Systems
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    Abstract. Portable digital systems tend to be not just low power but power efficient as they are powered by low batteries or energy harvesters. Energy harvesting systems tend to pr...
    Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yak...
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    167
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    A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC
    15 years 4 months ago
    A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC
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    Tanguy Sassolas, Nicolas Ventroux, Nassima Boudoua...
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    164
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    2010
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    An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs
    15 years 4 months ago
    An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs
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    Cristiano Lazzari, Jorge Fernandes, Paulo F. Flore...
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