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VLSID
2010
IEEE
211views VLSI» more  VLSID 2010»
15 years 5 months ago
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
VLSID
2010
IEEE
202views VLSI» more  VLSID 2010»
14 years 11 months ago
Processor Architecture Design Using 3D Integration Technology
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, is one of the promising solutions to mitigate the interconnect...
Yuan Xie
VLSID
2010
IEEE
200views VLSI» more  VLSID 2010»
14 years 11 months ago
Pinpointing Cache Timing Attacks on AES
The paper analyzes cache based timing attacks on optimized codes for Advanced Encryption Standard (AES). The work justifies that timing based cache attacks create hits in the fi...
Chester Rebeiro, Mainack Mondal, Debdeep Mukhopadh...
VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
14 years 11 months ago
Rethinking Threshold Voltage Assignment in 3D Multicore Designs
Due to the inherent nature of heat flow in 3D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The strong dependence of leakage with temperature...
Koushik Chakraborty, Sanghamitra Roy
VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
14 years 11 months ago
A Reconfigurable Architecture for Secure Multimedia Delivery
This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (D...
Amit Pande, Joseph Zambreno
VLSI
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