1834 search results - page 197 / 367 » A Dynamic Multithreading Processor |
161
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DATE
2007
IEEE
16 years 18 days ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
205
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ECRTS
2007
IEEE
16 years 18 days ago
2007
IEEE
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
159
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IPPS
2007
IEEE
16 years 17 days ago
2007
IEEE
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
202
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DAC
2009
ACM
15 years 11 months ago
2009
ACM
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
145
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...