This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
Patrick O'Neil Meredith, Michael Katelman, Jos&eac...
The paper addresses the formal specification, design and implementation of the behavioral component of graphical user interfaces. The complex sequences of visual events and action...
Jean Berstel, Stefano Crespi-Reghizzi, Gilles Rous...
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
Abstract We present a formal semantics as a conservative shallow embedding of the Object Constraint Language (OCL). OCL is currently under development within an open standardizatio...
–Abstract for conference - preliminary Model-Based Testing: Models for Test Cases Jan Tretmans, Embedded Systems Institute, Eindhoven : Systematic testing of software plays an im...