1420 search results - page 29 / 284 » A Framework for Scheduler Synthesis |
TCAD
2010
14 years 6 months ago
2010
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...
CODES
2007
IEEE
15 years 6 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
EURODAC
1994
IEEE
15 years 3 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
FPGA
2009
ACM
15 years 6 months ago
2009
ACM
In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research i...
ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
A leaf-level clock mesh is known to be very tolerant to variations [1]. However, its use is limited to a few high-end designs because of the high power/resource requirements and la...