160 search results - page 17 / 32 » A General Buffer Scheme for the Windows Scheduling Problem |
103
click to vote
WOWMOM
2006
ACM
15 years 5 months ago
2006
ACM
— In multihop wireless networks where a random access MAC scheme such as CSMA/CA is used, nodes greedily compete in a distributed manner and are unaware of the interference they ...
103
click to vote
CF
2005
ACM
15 years 1 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
217
click to vote
Publication
With increasingly widespread use of computer networks, and the use of varied technology for the interconnection of computers, congestion is a significant problem. In this report, w...
121
click to vote
ISCA
2012
IEEE
13 years 2 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
108
click to vote
MICRO
2005
IEEE
15 years 5 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...