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» A Network on Chip Architecture and Design Methodology
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DAC
2009
ACM
16 years 26 days ago
An SDRAM-aware router for Networks-on-Chip
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilizat...
Wooyoung Jang, David Z. Pan
IASTEDSEA
2004
15 years 1 months ago
Instance orientation: A programming methodology
Instance orientation is an approach for designing and programming software systems. It addresses a limitation of current software architectures: it allows multiple higherlevel vie...
Thomas Schöbel-Theuer
MICRO
2003
IEEE
99views Hardware» more  MICRO 2003»
15 years 5 months ago
Power-driven Design of Router Microarchitectures in On-chip Networks
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
IEEEPACT
2008
IEEE
15 years 6 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
DAC
1996
ACM
15 years 4 months ago
RTL Emulation: The Next Leap in System Verification
ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL ...
Sanjay Sawant, Paul Giordano