233 search results - page 12 / 47 » Address Code Generation for Digital Signal Processors |
LCTRTS
2007
Springer
15 years 5 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
ET
2002
14 years 11 months ago
2002
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
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ICS
2004
Tsinghua U.
15 years 4 months ago
2004
Tsinghua U.
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
ISSS
1999
IEEE
15 years 3 months ago
1999
IEEE
Abstract--Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs h...
DAC
1996
ACM
15 years 3 months ago
1996
ACM
In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer ...