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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 11 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
GLVLSI
2002
IEEE
109views VLSI» more  GLVLSI 2002»
15 years 11 months ago
Minimizing resources in a repeating schedule for a split-node data-flow graph
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
Timothy W. O'Neil, Edwin Hsing-Mean Sha
STOC
2003
ACM
110views Algorithms» more  STOC 2003»
16 years 6 months ago
New degree bounds for polynomial threshold functions
A real multivariate polynomial p(x1, . . . , xn) is said to sign-represent a Boolean function f : {0, 1}n {-1, 1} if the sign of p(x) equals f(x) for all inputs x {0, 1}n. We gi...
Ryan O'Donnell, Rocco A. Servedio
SCESM
2006
ACM
257views Algorithms» more  SCESM 2006»
16 years 7 days ago
Test ready UML statechart models
The dynamic behavior of systems is best described by Finite-state machines. Generation of executable tests from behavioral models such as UML Statecharts offers benefits such as s...
P. V. R. Murthy, P. C. Anitha, M. Mahesh, Rajesh S...
LCTRTS
2004
Springer
15 years 11 months ago
Dynamic voltage scaling for real-time multi-task scheduling using buffers
This paper proposes energy efficient real-time multi-task scheduling (EDF and RM) algorithms by using buffers. The buffering technique overcomes a drawback of previous approaches ...
Chaeseok Im, Soonhoi Ha