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» An Integrated Approach for Improving Cache Behavior
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154
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GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
14 years 7 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...
RTAS
2006
IEEE
15 years 3 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
SIGARCH
2008
96views more  SIGARCH 2008»
14 years 9 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
104
Voted
CODES
2011
IEEE
13 years 9 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
VLDB
2002
ACM
120views Database» more  VLDB 2002»
14 years 9 months ago
Improving Data Access of J2EE Applications by Exploiting Asynchronous Messaging and Caching Services
The J2EE platform provides a variety of options for making business data persistent using DBMS technology. However, the integration with existing backend database systems has prov...
Samuel Kounev, Alejandro P. Buchmann