220 search results - page 24 / 44 » An adaptive packed-memory array |
FPL
2004
Springer
15 years 3 months ago
2004
Springer
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
EH
2003
IEEE
15 years 3 months ago
2003
IEEE
The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectua...
ICIP
2007
IEEE
15 years 1 months ago
2007
IEEE
We present a computationally efficient demosaicing algorithm based on a luminance-chrominance model of the Color Filter Array (CFA) image. We show that the chrominance information ...
118
click to vote
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
100
click to vote
MASS
2010
14 years 7 months ago
2010
With the popularity of wireless devices and the increase of computing and storage resources, there are increasing interests in supporting mobile computing techniques. Particularly...