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» An improvement in formal verification
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MEMOCODE
2010
IEEE
14 years 10 months ago
A formal executable semantics of Verilog
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
Patrick O'Neil Meredith, Michael Katelman, Jos&eac...
EMSOFT
2006
Springer
15 years 2 months ago
Reusable models for timing and liveness analysis of middleware for distributed real-time and embedded systems
Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools ...
Venkita Subramonian, Christopher D. Gill, Cé...
JLP
2006
108views more  JLP 2006»
15 years 19 days ago
On testing UML statecharts
We present a formal framework for notions related to testing and model based test generation for a behavioural subset of UML Statecharts (UMLSCs). This framework builds, on one ha...
Mieke Massink, Diego Latella, Stefania Gnesi
FORTE
2009
14 years 10 months ago
Keep It Small, Keep It Real: Efficient Run-Time Verification of Web Service Compositions
Abstract. Service compositions leverage remote services to deliver addedvalue distributed applications. Since services are administered and run by independent parties, the governan...
Luciano Baresi, Domenico Bianculli, Sam Guinea, Pa...
CVPR
2007
IEEE
16 years 2 months ago
Offline Signature Verification Using Online Handwriting Registration
This paper proposes a novel framework for offline signature verification. Different from previous methods, our approach makes use of online handwriting instead of handwritten imag...
Yu Qiao, Jianzhuang Liu, Xiaoou Tang