3171 search results - page 448 / 635 » Application of Reduce Order Modeling to Time Parallelization |
227
Voted
DAC
2011
ACM
14 years 3 months ago
2011
ACM
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
107
Voted
SENSYS
2006
ACM
15 years 9 months ago
2006
ACM
Event-driven programming is a popular model for writing programs for tiny embedded systems and sensor network nodes. While event-driven programming can keep the memory overhead do...
132
Voted
ASPDAC
2008
ACM
15 years 5 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
126
Voted
LCTRTS
2009
Springer
15 years 10 months ago
2009
Springer
Embedded systems, like general-purpose systems, can benefit from parallel execution on a symmetric multicore platform. Unfortunately, concurrency issues present in general-purpos...
124
Voted
IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
The excessive complexity of both machine architectures and applications have made it difficult for compilers to statically model and predict application behavior. This observatio...