312 search results - page 12 / 63 » Architectural approaches to reduce leakage energy in caches |
IPPS
2007
IEEE
15 years 6 months ago
2007
IEEE
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
101
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DAC
2006
ACM
16 years 21 days ago
2006
ACM
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...
MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
112
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DAC
2007
ACM
16 years 22 days ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
103
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ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...