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» CX: A scalable, robust network for parallel computing
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SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
15 years 5 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
IEEEPACT
2008
IEEE
15 years 6 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
CF
2010
ACM
15 years 4 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
SIGCOMM
2010
ACM
14 years 12 months ago
Rethinking iBGP routing
The Internet is organized as a collection of administrative domains, known as Autonomous Systems (ASes). These ASes interact through the Border Gateway Protocol (BGP) that allows ...
Iuniana M. Oprescu, Mickael Meulle, Steve Uhlig, C...
108
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CIC
2003
150views Communications» more  CIC 2003»
15 years 1 months ago
Performance Modeling of a Cluster of Workstations
Using off-the-shelf commodity workstations to build a cluster for parallel computing has become a common practice. In studying or designing a cluster of workstations one should ha...
Ahmed M. Mohamed, Lester Lipsky, Reda A. Ammar