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OSDI
1996
ACM
15 years 5 months ago
A Trace-Driven Comparison of Algorithms for Parallel Prefetching and Caching
High-performance I/O systems depend on prefetching and caching in order to deliver good performance to applications. These two techniques have generally been considered in isolati...
Tracy Kimbrel, Andrew Tomkins, R. Hugo Patterson, ...
TVLSI
2008
150views more  TVLSI 2008»
15 years 3 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
IJES
2008
101views more  IJES 2008»
15 years 4 months ago
The Artemis workbench for system-level performance evaluation of embedded systems
In this article, we present an overview of the Artemis workbench, which provides modelling and simulation methods and tools for efficient performance evaluation and exploration of ...
Andy D. Pimentel
IPPS
2007
IEEE
15 years 10 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
CF
2007
ACM
15 years 8 months ago
Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols
In this work we reduce interconnect power dissipation in Symmetric Multiprocessors or SMPs. We revisit snoopy cache coherence protocols and reduce unnecessary interconnect activit...
Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai