Sciweavers

170 search results - page 8 / 34
» Challenges in Embedded Memory Design and Test
Sort
View
124
Voted
DAC
2000
ACM
16 years 4 months ago
Embedded hardware and software self-testing methodologies for processor cores
At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test m...
Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, ...
136
Voted
ICST
2008
IEEE
15 years 10 months ago
Designing and Building a Software Test Organization
–Abstract for conference - preliminary Model-Based Testing: Models for Test Cases Jan Tretmans, Embedded Systems Institute, Eindhoven : Systematic testing of software plays an im...
Bruce Benton
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
15 years 8 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
132
Voted
HIPEAC
2005
Springer
15 years 9 months ago
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
Ke Ning, David R. Kaeli
132
Voted
GLVLSI
2008
IEEE
157views VLSI» more  GLVLSI 2008»
15 years 10 months ago
Coverage-driven automatic test generation for uml activity diagrams
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita