14007 search results - page 15 / 2802 » Communications in Bus Networks |
FPGA
1995
ACM
15 years 1 months ago
1995
ACM
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Distributed systems, especially time-triggered ones, are implementing clock synchronization algorithms to provide and maintain a common view of time among the different nodes. S...
119
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
101
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HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
MOBICOM
2006
ACM
15 years 4 months ago
2006
ACM
Vehicular AdHoc Networks (VANET) can be treated as special kinds of Delay-tolerant Networks (DTN) where end-toend path might never be possible. As a result, mobile adhoc (MANET) r...