288 search results - page 41 / 58 » Comparing memory systems for chip multiprocessors |
ASPDAC
1995
ACM
15 years 3 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
119
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ISCA
2012
IEEE
13 years 2 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
127
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PPOPP
2006
ACM
15 years 5 months ago
2006
ACM
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
111
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IEEEPACT
2006
IEEE
15 years 5 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
ISCA
2007
IEEE
15 years 6 months ago
2007
IEEE
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...