931 search results - page 116 / 187 » Compiling for vector-thread architectures |
150
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DAC
2007
ACM
16 years 5 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
137
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VLSID
2009
IEEE
16 years 5 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
138
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ICASSP
2008
IEEE
15 years 11 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
162
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WCRE
2002
IEEE
15 years 9 months ago
2002
IEEE
The University of Queensland Binary Translator (UQBT ) is a static binary translation framework that allows for the translation of binary, executable programs, from one architectu...
139
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IEEEPACT
2000
IEEE
15 years 9 months ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...