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151
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ISHPC
1999
Springer
15 years 7 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
172
Voted
HPCA
1998
IEEE
15 years 7 months ago
Address Translation Mechanisms In Network Interfaces
Good network hardware performance is often squandered by overheads for accessing the network interface (NI) within a host. NIs that support user-level messaging avoid frequent ope...
Ioannis Schoinas, Mark D. Hill
179
Voted
ICDCS
1998
IEEE
15 years 7 months ago
A Feedback Based Scheme for Improving TCP Performance in Ad-Hoc Wireless Networks
Ad-hoc networks consist of a set of mobile hosts that communicate using wireless links, without the use of other communication support facilities (such as base stations). The topo...
Kartik Chandran, Sudarshan Raghunathan, S. Venkate...
ICNP
1998
IEEE
15 years 7 months ago
Darwin: Customizable Resource Management for Value-Added Network Services
The Internet is rapidly changing from a set of wires and switches that carry packets into a sophisticated infrastructure that delivers a set of complex value-added services to end...
Prashant R. Chandra, Allan Fisher, Corey Kosak, T....
136
Voted
SPAA
1998
ACM
15 years 7 months ago
Lamport Clocks: Verifying a Directory Cache-Coherence Protocol
Modern shared-memory multiprocessors use complex memory system implementations that include a variety of non-trivial and interacting optimizations. More time is spent in verifying...
Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D...
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