Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Abstract—Network power consumption can be reduced considerably by adapting link data rates to their offered traffic loads. In this paper, we exploit how to leverage rate adaptat...
The Densest k-subgraph problem (i.e. find a size k subgraph with maximum number of edges), is one of the notorious problems in approximation algorithms. There is a significant g...
vel Meta-Reasoning with Higher-Order Abstract Syntax Alberto Momigliano, Simon Ambler. A Normalisation Result for Higher-Order Calculi with Explicit Substitutions Eduardo Bonelli. ...