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ET
2002
115views more  ET 2002»
15 years 2 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
TVLSI
2010
14 years 9 months ago
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-
Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are ...
Hai Lin, Yunsi Fei, Xuan Guan, Zhijie Jerry Shi
150
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MUC
1992
15 years 7 months ago
GE NLToolset: description of the system as used for MUC-4
The GE NLTooLsET is a set of text interpretation tools designed to be easily adapted to new domains. This report summarizes the system and its performance on the MUG-4 task . INTR...
George B. Krupka, Paul S. Jacobs, Lisa F. Rau, Loi...
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
15 years 7 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
ASIAMS
2007
IEEE
15 years 9 months ago
XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks
Simulation is perhaps the most cost-effective tool to evaluate the operation of a system under design. A flexible, easy to extend, fully object-oriented, and multilayered simulato...
Abbas Nayebi, Sina Meraji, Arash Shamaei, Hamid Sa...