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» Coordination Patterns for Parallel Computing
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107
Voted
IPPS
2007
IEEE
15 years 6 months ago
Optimizing Inter-Nest Data Locality Using Loop Splitting and Reordering
With the increasing gap between processor speed and memory latency, the performance of data-dominated programs are becoming more reliant on fast data access, which can be improved...
Sofiane Naci
NOCS
2007
IEEE
15 years 6 months ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
97
Voted
HPCC
2007
Springer
15 years 6 months ago
Towards Scalable and High Performance I/O Virtualization - A Case Study
I/O Virtualization provides a convenient way of device sharing among guest domains in a virtualized platform (e.g. Xen). However, with the ever-increasing number and variety of dev...
Jinpeng Wei, Jeffrey R. Jackson, John A. Wiegert
107
Voted
IPPS
2006
IEEE
15 years 6 months ago
Coterminous locality and coterminous group data prefetching on chip-multiprocessors
Due to shared cache contentions and interconnect delays, data prefetching is more critical in alleviating penalties from increasing memory latencies and demands on Chip-Multiproce...
Xudong Shi, Zhen Yang, Jih-Kwon Peir, Lu Peng, Yen...
IPPS
2006
IEEE
15 years 6 months ago
A segment-based DSM supporting large shared object space
This paper introduces a software DSM that can extend its shared object space exceeding 4GB in a 32bit commodity cluster environment. This is achieved through the dynamic memory ma...
Benny Wang-Leung Cheung, Cho-Li Wang