145 search results - page 15 / 29 » Datapath Scheduling using Dynamic Frequency Clocking |
80
Voted
ICCD
2001
IEEE
15 years 6 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
84
Voted
TWC
2008
14 years 9 months ago
2008
Abstract--In this paper, the flow-level performance of opportunistic scheduling in orthogonal frequency division multiplexing (OFDM) networks is studied. The analysis accounts for ...
FPGA
2009
ACM
15 years 4 months ago
2009
ACM
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...
91
Voted
RSP
2003
IEEE
15 years 2 months ago
2003
IEEE
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
TVLSI
2008
14 years 9 months ago
2008
Thermal hot spots and high temperature gradients degrade reliability and performance, and increase cooling costs and leakage power. In this paper, we explore the benefits of temper...