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CODES
2011
IEEE
14 years 5 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
CODES
2006
IEEE
15 years 11 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
IWMM
2004
Springer
101views Hardware» more  IWMM 2004»
15 years 11 months ago
Exploring the barrier to entry: incremental generational garbage collection for Haskell
We document the design and implementation of a “production” incremental garbage collector for GHC 6.2. It builds on our earlier work (Non-stop Haskell) that exploited GHC’s ...
Andrew M. Cheadle, A. J. Field, Simon Marlow, Simo...
DIGRA
2003
Springer
15 years 10 months ago
The Construction of Ludic Space
Most modern graphics-based computer games entertain the player in part by presenting him or her with a simulated space, an imaginary two- or threedimensional region whose visual a...
Ernest Adams
CODES
2003
IEEE
15 years 10 months ago
A multiobjective optimization model for exploring multiprocessor mappings of process networks
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...
Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel