150 search results - page 5 / 30 » Design and CAD for 3D integrated circuits |
ISQED
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
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ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
ICCAD
2010
IEEE
14 years 7 months ago
2010
IEEE
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
— The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footpr...
CASES
2010
ACM
14 years 7 months ago
2010
ACM
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...