8345 search results - page 1628 / 1669 » Design of Neuromorphic Hardwares |
141
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CODES
2007
IEEE
15 years 8 months ago
2007
IEEE
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
129
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CODES
2007
IEEE
15 years 8 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
134
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CODES
2007
IEEE
15 years 8 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
133
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DSN
2007
IEEE
15 years 8 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
128
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HPDC
2007
IEEE
15 years 8 months ago
2007
IEEE
Grid computations require global access to massive data stores. To meet this need, the GridNFS project aims to provide scalable, high-performance, transparent, and secure wide-are...