453 search results - page 57 / 91 » Designing hardware with dynamic memory abstraction |
HIPEAC
2009
Springer
15 years 1 months ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
DSD
2004
IEEE
15 years 1 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
ISER
2000
Springer
15 years 1 months ago
2000
Springer
Abstract: The paper describes the humanoid robot \H6", which was designed to serve as a platform for experimental research on the development of advanced humanoid-type robots....
FPGA
2005
ACM
15 years 3 months ago
2005
ACM
Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with m...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...