261 search results - page 27 / 53 » Effect of time delay on telesurgical performance |
ET
2002
14 years 11 months ago
2002
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
ICCD
2000
IEEE
15 years 8 months ago
2000
IEEE
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presen...
ASPDAC
2006
ACM
15 years 5 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
ASPDAC
2006
ACM
15 years 5 months ago
2006
ACM
— Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the numbe...
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IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
Innovative scientific applications and emerging dense data sources are creating a data deluge for highend computing systems. Processing such large input data typically involves cop...