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» Efficient stereo-to-multiview synthesis
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97
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FPL
2006
Springer
147views Hardware» more  FPL 2006»
15 years 1 months ago
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
EURODAC
1995
IEEE
134views VHDL» more  EURODAC 1995»
15 years 1 months ago
Area efficient DSP datapath synthesis
Andrew A. Duncan, David C. Hendry
ASPDAC
2008
ACM
89views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Efficient synthesis of compressor trees on FPGAs
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
14 years 10 months ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
84
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DSD
2009
IEEE
88views Hardware» more  DSD 2009»
14 years 7 months ago
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
Abstract--The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer an...
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana