Sciweavers

1957 search results - page 204 / 392
» Embedded Processor Security
Sort
View
ECRTS
2010
IEEE
15 years 7 months ago
Partitioning Parallel Applications on Multiprocessor Reservations
A full exploitation of the computational power available in a multi-core platform requires the software to be specified in terms of parallel execution flows. At the same time, mode...
Giorgio C. Buttazzo, Enrico Bini, Yifan Wu
ISW
2009
Springer
16 years 26 days ago
MAC Precomputation with Applications to Secure Memory
We present ShMAC (Shallow MAC), a fixed input length message authentication code that performs most of the computation prior to the availability of the message. Specifically, Sh...
Juan A. Garay, Vladimir Kolesnikov, Rae McLellan
APCSAC
2001
IEEE
15 years 10 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
CASES
2001
ACM
15 years 10 months ago
Application specific architectures: a recipe for fast, flexible and power efficient designs
The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent ...
Christopher T. Weaver, Rajeev Krishna, Lisa Wu, To...
SIES
2009
IEEE
16 years 1 months ago
A flexible design flow for software IP binding in commodity FPGA
— Software intellectual property (SWIP) is a critical component of increasingly complex FPGA based system on chip (SOC) designs. As a result, developers want to ensure that their...
Michael Gora, Abhranil Maiti, Patrick Schaumont