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DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
15 years 4 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
ICC
2007
IEEE
110views Communications» more  ICC 2007»
15 years 4 months ago
Resource Optimization to Provision a Virtual Private Network Using the Hose Model
— Virtual Private Networks (VPN) provide a secure and reliable communication between customer sites over a shared network. With increase in number and size of VPNs, providers nee...
Monia Ghobadi, Sudhakar Ganti, Gholamali C. Shoja
ICSNC
2007
IEEE
15 years 4 months ago
Movement Prediction Using Bayesian Learning for Neural Networks
Nowadays, path prediction is being extensively examined for use in the context of mobile and wireless computing towards more efficient network resource management schemes. Path pr...
Sherif Akoush, Ahmed Sameh
IPPS
2007
IEEE
15 years 4 months ago
Experience of Optimizing FFT on Intel Architectures
Automatic library generators, such as ATLAS [11], Spiral [8] and FFTW [2], are promising technologies to generate efficient code for different computer architectures. The library...
Daniel Orozco, Liping Xue, Murat Bolat, Xiaoming L...
GLOBECOM
2007
IEEE
15 years 4 months ago
Path Diversity in Packet Switched Networks: Performance Analysis and Rate Allocation
—Path diversity works by setting up multiple parallel connections between the end points using the topological path redundancy of the network. In this paper, Forward Error Correc...
Shervan Fashandi, Shahab Oveis Gharan, Amir K. Kha...