1534 search results - page 47 / 307 » Error Reporting Logic |
CEC
2008
IEEE
15 years 4 months ago
2008
IEEE
Abstract— Model Checking is a well-known and fully automatic technique for checking software properties, usually given as temporal logic formulae on the program variables. Most o...
DFT
2008
IEEE
15 years 4 months ago
2008
IEEE
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
VTS
2007
IEEE
15 years 4 months ago
2007
IEEE
Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. In this paper we analyze the soft error vulnerability of FPGAs used in storage systems. Sinc...
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
ISQED
2006
IEEE
15 years 4 months ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...