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ERSA
2006
132views Hardware» more  ERSA 2006»
14 years 11 months ago
Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers
: A brief review of mapping generalized template matching operations onto reconfigurable computers is given. A combinatorial optimization process, where the objective is to minimiz...
Xuejun Liang, Qutaibah M. Malluhi
SIES
2009
IEEE
15 years 4 months ago
A flexible design flow for software IP binding in commodity FPGA
— Software intellectual property (SWIP) is a critical component of increasingly complex FPGA based system on chip (SOC) designs. As a result, developers want to ensure that their...
Michael Gora, Abhranil Maiti, Patrick Schaumont
FCCM
2007
IEEE
117views VLSI» more  FCCM 2007»
15 years 4 months ago
FPGA Acceleration of Gene Rearrangement Analysis
In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and co...
Jason D. Bakos
FPGA
2005
ACM
174views FPGA» more  FPGA 2005»
15 years 3 months ago
64-bit floating-point FPGA matrix multiplication
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G...
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
15 years 3 months ago
In-system FPGA prototyping of an itanium microarchitecture
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
Roland E. Wunderlich, James C. Hoe